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author | Max Krummenacher <max.krummenacher@toradex.com> | 2018-12-06 09:43:37 +0100 |
---|---|---|
committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2020-02-09 22:45:43 +0100 |
commit | f56c26d4734519b3bff0d706e4db566c163a120e (patch) | |
tree | 4bae13d3b56843eab3ead87b415ab29eaf98c0c1 /arch/arm/boot/dts/imx6ull-colibri.dtsi | |
parent | afec02777f94282e911c5138d18c08a9ab8b61a1 (diff) |
ARM: dts: imx6ull: improve can templates
Add the pinmuxing and a inactive node for flexcan1 on SODIMM 55/63
and move the inactive flexcan modes to imx6ull-colibri-eval-v3.dtsi
where they belong.
Note that this commit does not enable flexcan functionality, but rather
eases the effort needed to do so.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
(cherry picked from commit 983ff8a6b61e9466beb6b4781fb370a6a7da937a)
Conflicts:
arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
arch/arm/boot/dts/imx6ull-colibri.dtsi
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com
Diffstat (limited to 'arch/arm/boot/dts/imx6ull-colibri.dtsi')
-rw-r--r-- | arch/arm/boot/dts/imx6ull-colibri.dtsi | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index ce4b07bef16d..bbc49c4ccb32 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -252,6 +252,13 @@ >; }; + pinctrl_flexcan1: flexcan1-grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 + >; + }; + pinctrl_flexcan2: flexcan2-grp { fsl,pins = < MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 @@ -267,8 +274,6 @@ pinctrl_gpio1: gpio1-grp { fsl,pins = < - MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */ - MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */ MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0X14 /* SODIMM 77 */ MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x14 /* SODIMM 99 */ MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x14 /* SODIMM 133 */ @@ -321,6 +326,13 @@ >; }; + pinctrl_gpio7: gpio7-grp { /* CAN1 */ + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */ + MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */ + >; + }; + pinctrl_gpmi_nand: gpmi-nand-grp { fsl,pins = < MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 |