diff options
| author | Stefan Agner <stefan@agner.ch> | 2017-12-19 19:10:37 +0100 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2020-02-09 22:45:40 +0100 |
| commit | db349c64b3834389dd4107239c314588634daa82 (patch) | |
| tree | a511a4d1882e9532b8c464a765c81b734da7b222 /arch/arm/boot/dts/imx7-colibri.dtsi | |
| parent | 66e3d4ed9f1b4b47ca3879d817cd859d5329242d (diff) | |
ARM: dts: imx7-colibri: add MCP2515 CAN controller
The Colibri Evaluation Carrier Board provides a MCP2515 CAN
controller connected via SPI. Note that the i.MX 7 provides
an internal CAN controller which is much better suited for CAN
operations. Using the MCP2515 with a Colibri iMX7 module is
mainly useful to test the SPI interface.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
(cherry picked from commit 66d59b678a87152f85dd327ba6aa024df2896b37)
Diffstat (limited to 'arch/arm/boot/dts/imx7-colibri.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx7-colibri.dtsi | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index bcecdb361707..98f826cf1232 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -92,6 +92,12 @@ cpu-supply = <®_DCDC2>; }; +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>; + cs-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; @@ -313,7 +319,6 @@ fsl,pins = < MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x74 /* SODIMM 55 */ MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x74 /* SODIMM 63 */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */ MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */ MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */ MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */ @@ -400,6 +405,12 @@ >; }; + pinctrl_can_int: can-int-grp { + fsl,pins = < + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */ + >; + }; + pinctrl_enet1: enet1grp { fsl,pins = < MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 |