diff options
| author | Haibo Chen <haibo.chen@nxp.com> | 2019-05-17 15:27:44 +0800 |
|---|---|---|
| committer | Haibo Chen <haibo.chen@nxp.com> | 2019-05-21 15:07:34 +0800 |
| commit | ef369313de747251ff11c108e7fd5bf2b92df603 (patch) | |
| tree | 89e36fd02915b3e09071ba19f91b2a316f4f6ac5 /arch/arm/boot/dts/imx7ulp-evk.dts | |
| parent | 17e7a59b68fbaa599d2f761a5c8c1f4c77284f7a (diff) | |
MLK-20420 ARM: dts: imx7ulp-evk: add delay cell for DDR50/DDR52 mode
We find some imx7ulp evk board, SD card work in DDR50 mode will meet
data CRC error. Only some board has this issue. And eMMC DDR50 mode
also has this issue on these boards. For DDR50, do tuning can fix
this issue, but eMMC DDR52 do not support tuning. So this patch
manually add the delay cell on the fixed clock (FBCLK_SEL = 0).
Currently, add 15 delay cell, which can make DDR50/DDR52 works stable
on all imx7ulp evk board.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx7ulp-evk.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx7ulp-evk.dts | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts index 366abe6fedcc..fe215e5a998a 100644 --- a/arch/arm/boot/dts/imx7ulp-evk.dts +++ b/arch/arm/boot/dts/imx7ulp-evk.dts @@ -559,6 +559,7 @@ pinctrl-1 = <&pinctrl_usdhc0>; pinctrl-2 = <&pinctrl_usdhc0>; pinctrl-3 = <&pinctrl_usdhc0>; + fsl,delay-line = <15>; cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>; vmmc-supply = <®_vsd_3v3>; vqmmc-supply = <&vldo2_reg>; |