diff options
| author | Dong Aisheng <aisheng.dong@nxp.com> | 2017-09-07 22:02:03 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:30:35 +0800 |
| commit | d51c3401b554daf2556f266cefd6db8e5831b237 (patch) | |
| tree | 150a431d2da514857cbf64bdefa5054828b0c9c4 /arch/arm/boot/dts/imx7ulp.dtsi | |
| parent | 73129e81393dc04e7ef2af371d3f20bd842406f2 (diff) | |
MLK-17491-48 clk: imx7ulp: fix the wrong periph_bus_sels clocks
According to the clk digram in section 24.6 Core, Platform and System Bus
clocks in reference manual, the correct available periph_bus_sels should be
{ "dummy", "sosc_bus_clk", "mpll", "firc_bus_clk", "rosc", "nic1_bus",
"nic1_div", "spll_bus_clk", }.
And the real tpm/pwm/lpuart parent clock should be IMX7ULP_CLK_SOSC_BUS_CLK
while some others should be IMX7ULP_CLK_FIRC_BUS_CLK, So update dts as well.
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx7ulp.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx7ulp.dtsi | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index a7909b8c05c2..9e912809d2f8 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -202,7 +202,7 @@ reg = <0x40250000 0x1000>; nxp,pwm-number = <6>; assigned-clocks = <&clks IMX7ULP_CLK_LPTPM4>; - assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC>; + assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC_BUS_CLK>; clocks = <&clks IMX7ULP_CLK_LPTPM4>; #pwm-cells = <2>; }; @@ -224,7 +224,7 @@ clocks = <&clks IMX7ULP_CLK_LPIT1>; assigned-clock-rates = <48000000>; assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>; - assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>; }; lpi2c4: lpi2c4@402B0000 { @@ -235,7 +235,7 @@ <&clks IMX7ULP_CLK_NIC1_BUS_DIV>; clock-names = "per", "ipg"; assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>; - assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; status = "disabled"; }; @@ -248,7 +248,7 @@ <&clks IMX7ULP_CLK_NIC1_BUS_DIV>; clock-names = "per", "ipg"; assigned-clocks = <&clks IMX7ULP_CLK_LPI2C5>; - assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; }; @@ -259,7 +259,7 @@ clocks = <&clks IMX7ULP_CLK_LPSPI2>; clock-names = "ipg"; assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>; - assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; status = "disabled"; }; @@ -271,7 +271,7 @@ clocks = <&clks IMX7ULP_CLK_LPSPI3>; clock-names = "ipg"; assigned-clocks = <&clks IMX7ULP_CLK_LPSPI3>; - assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; status = "disabled"; }; @@ -283,7 +283,7 @@ clocks = <&clks IMX7ULP_CLK_LPUART4>; clock-names = "ipg"; assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>; - assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC>; + assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC_BUS_CLK>; assigned-clock-rates = <24000000>; status = "disabled"; }; @@ -295,7 +295,7 @@ clocks = <&clks IMX7ULP_CLK_LPUART5>; clock-names = "ipg"; assigned-clocks = <&clks IMX7ULP_CLK_LPUART5>; - assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; dmas = <&edma0 0 20>, <&edma0 0 19>; dma-names = "tx","rx"; @@ -366,7 +366,7 @@ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX7ULP_CLK_WDG1>; assigned-clocks = <&clks IMX7ULP_CLK_WDG1>; - assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>; /* * As the 1KHz LPO clock rate is not trimed,the actually clock * is about 667Hz, so the init timeout 60s should set 40*1000 @@ -381,7 +381,7 @@ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX7ULP_CLK_WDG2>; assigned-clocks = <&clks IMX7ULP_CLK_WDG2>; - assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>; timeout-sec = <40>; }; @@ -395,7 +395,7 @@ #clock-cells = <1>; assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>, <&clks IMX7ULP_CLK_USDHC1>; - assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC>, + assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC_BUS_CLK>, <&clks IMX7ULP_CLK_NIC1_DIV>; }; @@ -431,7 +431,7 @@ <&clks IMX7ULP_CLK_NIC1_BUS_DIV>; clock-names = "per", "ipg"; assigned-clocks = <&clks IMX7ULP_CLK_LPI2C6>; - assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; status = "disabled"; }; @@ -444,7 +444,7 @@ <&clks IMX7ULP_CLK_NIC1_BUS_DIV>; clock-names = "per", "ipg"; assigned-clocks = <&clks IMX7ULP_CLK_LPI2C7>; - assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; status = "disabled"; }; @@ -456,7 +456,7 @@ clocks = <&clks IMX7ULP_CLK_LPUART6>; clock-names = "ipg"; assigned-clocks = <&clks IMX7ULP_CLK_LPUART6>; - assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; dmas = <&edma0 0 22>, <&edma0 0 21>; dma-names = "tx","rx"; @@ -470,7 +470,7 @@ clocks = <&clks IMX7ULP_CLK_LPUART7>; clock-names = "ipg"; assigned-clocks = <&clks IMX7ULP_CLK_LPUART7>; - assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; dmas = <&edma0 0 24>, <&edma0 0 23>; dma-names = "tx","rx"; |