diff options
| author | Dong Aisheng <aisheng.dong@nxp.com> | 2017-09-06 22:35:44 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:30:31 +0800 |
| commit | 244929edff61c8b97be3c21ea287e9fcfeca3bc0 (patch) | |
| tree | a217746a2cbb580fb4cd28ad14b1343e691d0964 /arch/arm/boot/dts/imx7ulp.dtsi | |
| parent | b6c414407ec94668d96ebef211f422fdd83b0e48 (diff) | |
MLK-17491-21 clk: imx7ulp: fix RTC OSC clock name
'CKIL' clock name is derived from MX6 SoC series which is invalid for
MX7ULP (can't find it from RM). Changing it to the correct 'ROSC'
which is defined in RM.
The exist 'OSC' name is also changed accordingly which should be SOSC
(System OSC).
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx7ulp.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx7ulp.dtsi | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index 32822046501d..a7909b8c05c2 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -94,18 +94,18 @@ #address-cells = <1>; #size-cells = <0>; - ckil: clock@0 { + rosc: clock@0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; - clock-output-names = "ckil"; + clock-output-names = "rosc"; }; - osc: clock@1 { + sosc: clock@1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; - clock-output-names = "osc"; + clock-output-names = "sosc"; }; sirc: clock@2 { @@ -202,7 +202,7 @@ reg = <0x40250000 0x1000>; nxp,pwm-number = <6>; assigned-clocks = <&clks IMX7ULP_CLK_LPTPM4>; - assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>; + assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC>; clocks = <&clks IMX7ULP_CLK_LPTPM4>; #pwm-cells = <2>; }; @@ -283,7 +283,7 @@ clocks = <&clks IMX7ULP_CLK_LPUART4>; clock-names = "ipg"; assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>; - assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>; + assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC>; assigned-clock-rates = <24000000>; status = "disabled"; }; @@ -388,14 +388,14 @@ clks: scg1@403E0000 { compatible = "fsl,imx7ulp-scg1"; reg = <0x403E0000 0x10000>; - clocks = <&ckil>, <&osc>, <&sirc>, + clocks = <&rosc>, <&sosc>, <&sirc>, <&firc>, <&upll>, <&mpll>; - clock-names = "ckil", "osc", "sirc", + clock-names = "rosc", "sosc", "sirc", "firc", "upll", "mpll"; #clock-cells = <1>; assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>, <&clks IMX7ULP_CLK_USDHC1>; - assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>, + assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC>, <&clks IMX7ULP_CLK_NIC1_DIV>; }; |