diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2017-12-26 20:31:46 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:30:03 +0800 |
| commit | 5680da75c8bb1214f475cacf7a65ef6069c6dbbe (patch) | |
| tree | 43b64dd61eb7c77c543f5a9fa27b4462a5c354f7 /arch/arm/boot/dts/imx7ulp.dtsi | |
| parent | fc5f2f3862c3d8a651f31e292b80d8bb6d586097 (diff) | |
MLK-17293-7 arm: dts: imx7ulp: update cpu set-points
According to datasheet Rev-D, on B0 part, below CPU
freq needs to be supported:
500MHz for RUN mode;
720MHz for HSRUN mode.
Update opp table accordingly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx7ulp.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx7ulp.dtsi | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index 2fb65e82ab5e..201ff09e86e2 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -43,8 +43,8 @@ operating-points = < /* KHz uV */ - 531648 1125000 - 416072 1025000 + 720000 1125000 + 500210 1025000 >; clocks = <&clks IMX7ULP_CLK_ARM>, <&clks IMX7ULP_CLK_CORE_DIV>, @@ -53,9 +53,11 @@ <&clks IMX7ULP_CLK_HSRUN_CORE>, <&clks IMX7ULP_CLK_SPLL_PFD0>, <&clks IMX7ULP_CLK_SPLL_SEL>, - <&clks IMX7ULP_CLK_FIRC>; + <&clks IMX7ULP_CLK_FIRC>, + <&clks IMX7ULP_CLK_SPLL>; clock-names = "arm", "core_div", "sys_sel", "hsrun_sys_sel", - "hsrun_core", "spll_pfd0", "spll_sel", "firc"; + "hsrun_core", "spll_pfd0", "spll_sel", "firc", + "spll"; }; }; |