diff options
| author | Bai Ping <ping.bai@nxp.com> | 2017-02-13 16:24:36 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:25:51 +0800 |
| commit | 6e150510ef8c5513ac392d3ae78a5ecb43f79c68 (patch) | |
| tree | c180fcaf5448832936846442b02375f397a10978 /arch/arm/boot/dts/imx7ulp.dtsi | |
| parent | eb7ec16cc64c28343d8607188023c78d6389045e (diff) | |
MLK-13914-03 ARM: dts: Add cpu setpoints and clocks properties on i.mx7ulp
Add CPU setpoints property on i.MX7ULP A0 part, the setpoints table is a preliminary
one, will update it according to the datasheet when the final one is available.
The setpoints we can currently used is as below:
416072 KHz/0.925V,
531648 KHz/1.025V;
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx7ulp.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx7ulp.dtsi | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index 6ec834bd6434..dc7e8efdfcbb 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -37,7 +37,24 @@ cpu0: cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; + clock-latency = <61036>; /* two CLK32 periods */ reg = <0>; + + operating-points = < + /* KHz uV */ + 531648 1025000 + 416072 925000 + >; + clocks = <&clks IMX7ULP_CLK_ARM>, + <&clks IMX7ULP_CLK_CORE_DIV>, + <&clks IMX7ULP_CLK_SYS_SEL>, + <&clks IMX7ULP_CLK_HSRUN_SYS_SEL>, + <&clks IMX7ULP_CLK_HSRUN_CORE>, + <&clks IMX7ULP_CLK_SPLL_PFD0>, + <&clks IMX7ULP_CLK_SPLL_SEL>, + <&clks IMX7ULP_CLK_FIRC>; + clock-names = "arm", "core_div", "sys_sel", "hsrun_sys_sel", + "hsrun_core", "spll_pfd0", "spll_sel", "firc"; }; }; |