diff options
| author | Andy Duan <fugang.duan@nxp.com> | 2016-11-09 09:48:30 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:25:18 +0800 |
| commit | d35712d2ff0833637052c275936b14154244236f (patch) | |
| tree | 8c67ebee6a0484ea7f86fd4670c8806f2f84f484 /arch/arm/boot/dts/imx7ulp.dtsi | |
| parent | 7c8d4589e689fbe3b674da7b1f9f1fbac09e1656 (diff) | |
MLK-13485-2 ARM: dts: imx7ulp: add GPIO support
Add GPIO (PCTLC,D,E,F) support
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx7ulp.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx7ulp.dtsi | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index 640f69de56e7..39526a1bedaf 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -15,6 +15,10 @@ interrupt-parent = <&intc>; aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; serial0 = &lpuart4; serial1 = &lpuart6; serial2 = &lpuart5; @@ -408,6 +412,50 @@ fsl,mux_mask = <0xf00>; }; + gpio0: gpio@40ae0000 { + compatible = "fsl,vf610-gpio"; + reg = <0x40ae0000 0x1000 0x400F0000 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc1 0 0 32>; + }; + + gpio1: gpio@40af0000 { + compatible = "fsl,vf610-gpio"; + reg = <0x40af0000 0x1000 0x400F0040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc1 0 32 32>; + }; + + gpio2: gpio@40b00000 { + compatible = "fsl,vf610-gpio"; + reg = <0x40b00000 0x1000 0x400F0080 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc1 0 64 32>; + }; + + gpio3: gpio@40b10000 { + compatible = "fsl,vf610-gpio"; + reg = <0x40b10000 0x1000 0x400F00c0 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc1 0 96 32>; + }; + pmc0: pmc0@410a1000 { compatible = "fsl,imx7ulp-pmc0"; reg = <0x410a1000 0x1000>; |