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| author | Shengjiu Wang <shengjiu.wang@freescale.com> | 2016-10-24 10:15:37 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:25:24 +0800 |
| commit | f396ed864cb6062a4e9e59d8e9e87f0aad87c678 (patch) | |
| tree | c766c80c5fcae5e38f523ea1227d87d03d131f54 /arch/arm/boot/dts/imx7ulp.dtsi | |
| parent | f5e946a7e93e5366db2d6150d07b8cba315b0197 (diff) | |
MLK-13418: ASoC: wm8960: workaround no sound issue in master mode
The input MCLK is 12.288MHz, The desired output sysclk is 11.2896MHz
the sample rate is 44100Hz, with the pllprescale=2, postscale=sysclkdiv=1,
some chip may have wrong bclk and lrclk output in master mode. then there
will be no sound.
With the pllprescale=1, postscale=2, the output clock is correct. so use
this configuration to workaround this issue.
Tested 8k/11k/16k/22k/32k/44k/48kHz case.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Diffstat (limited to 'arch/arm/boot/dts/imx7ulp.dtsi')
0 files changed, 0 insertions, 0 deletions