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| author | Anson Huang <Anson.Huang@nxp.com> | 2017-12-26 20:25:52 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:30:03 +0800 |
| commit | fc5f2f3862c3d8a651f31e292b80d8bb6d586097 (patch) | |
| tree | 34377a71a6f5bc62acc572d683cbaa8465ac5835 /arch/arm/boot/dts/imx7ulp.dtsi | |
| parent | e539f251becb780febe1deb0e21dd2cf27b5861d (diff) | |
MLK-17293-6 cpufreq: imx7ulp: support new set-points
According to datasheet Rev-D, on B0 part, below CPU
freq needs to be supported:
500MHz for RUN mode;
720MHz for HSRUN mode.
To achieve best accurate frequency for CPU, adjust
SPLL's frequency for SPLL_PFD0 which is CPU's
clock source:
SPLL 528MHz -> SPLL_PFD0 500.2MHz;
SPLL 480MHz -> SPLL_PFD0 720MHz;
Remove CPU RUN/HSRUN mode switch, since it is implemented
as clock mux, whenever clock parent is switched, the
RUN/HSRUN mode will be changed accordingly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx7ulp.dtsi')
0 files changed, 0 insertions, 0 deletions