diff options
| author | Sean Wang <sean.wang@mediatek.com> | 2017-08-01 15:03:29 +0800 |
|---|---|---|
| committer | Matthias Brugger <matthias.bgg@gmail.com> | 2017-08-01 15:52:10 +0200 |
| commit | 7aa125babf143d3c48b9e1be9871d9be175f9194 (patch) | |
| tree | 204a99438e5bd6f17ad8ae00f240e9f363b54df1 /arch/arm/boot/dts/mt2701.dtsi | |
| parent | 63edf128078152b4b719b1f5328b52b87d02a705 (diff) | |
arm: dts: mt2701: Add ethernet device node
Add ethernet device node for MT2701
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts/mt2701.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/mt2701.dtsi | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index f1efdc63656a..0619b86afaee 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -597,6 +597,30 @@ #clock-cells = <1>; }; + eth: ethernet@1b100000 { + compatible = "mediatek,mt2701-eth", "syscon"; + reg = <0 0x1b100000 0 0x20000>; + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <ðsys CLK_ETHSYS_ESW>, + <ðsys CLK_ETHSYS_GP1>, + <ðsys CLK_ETHSYS_GP2>, + <&apmixedsys CLK_APMIXED_TRGPLL>; + clock-names = "ethif", "esw", "gp1", "gp2", "trgpll"; + resets = <ðsys MT2701_ETHSYS_FE_RST>, + <ðsys MT2701_ETHSYS_GMAC_RST>, + <ðsys MT2701_ETHSYS_PPE_RST>; + reset-names = "fe", "gmac", "ppe"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; + mediatek,ethsys = <ðsys>; + mediatek,pctl = <&syscfg_pctl_a>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + bdpsys: syscon@1c000000 { compatible = "mediatek,mt2701-bdpsys", "syscon"; reg = <0 0x1c000000 0 0x1000>; |