diff options
| author | Tony Lindgren <tony@atomide.com> | 2014-09-18 09:03:36 -0700 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2014-09-18 09:03:36 -0700 |
| commit | 271d4c6bc709d922e5f8913bcb64d6c53a752e31 (patch) | |
| tree | a3deef7d05862e062d69bba8a043a126b13f7ee3 /arch/arm/boot/dts/omap3-n900.dts | |
| parent | a4ff93c185787412936bc8414f14f50bdd56e546 (diff) | |
ARM: dts: Add support for Ethernet on some N900 macro boards
As we have support for this in board-rx51-peripherals.c, let's
add it to the .dts files too.
Note that the reset GPIO will eventually go to the driver.
For now let's just pull it down and skip any further reset
in case the bootloader has configured the MAC address so
NFSroot works.
Also note that after 3430-sdp are using proper GPMC timings
we can remove the tests for smsc,lan91c94 in gpmc.c.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/omap3-n900.dts')
| -rw-r--r-- | arch/arm/boot/dts/omap3-n900.dts | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index f0d82369ef13..19a585773abe 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -134,6 +134,14 @@ >; }; + ethernet_pins: pinmux_ethernet_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */ + OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */ + >; + }; + i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < 0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl */ @@ -578,6 +586,8 @@ &gpmc { ranges = <0 0 0x04000000 0x10000000>; /* 256MB */ + ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */ + <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */ /* gpio-irq for dma: 65 */ @@ -646,6 +656,38 @@ reg = <0x004c0000 0x0fb40000>; }; }; + + ethernet@gpmc { + compatible = "smsc,lan91c94"; + interrupt-parent = <&gpio2>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */ + reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */ + bank-width = <2>; + pinctrl-names = "default"; + pinctrl-0 = <ðernet_pins>; + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <48>; + gpmc,cs-wr-off-ns = <24>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <0>; + gpmc,adv-wr-off-ns = <0>; + gpmc,we-on-ns = <12>; + gpmc,we-off-ns = <18>; + gpmc,oe-on-ns = <12>; + gpmc,oe-off-ns = <48>; + gpmc,page-burst-access-ns = <0>; + gpmc,access-ns = <42>; + gpmc,rd-cycle-ns = <180>; + gpmc,wr-cycle-ns = <180>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <0>; + gpmc,wr-data-mux-bus-ns = <12>; + }; }; &mcspi1 { |