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authorSuman Anna <s-anna@ti.com>2017-06-07 16:27:25 -0500
committerTony Lindgren <tony@atomide.com>2017-06-12 03:03:30 -0700
commitc8ceb5ac1ac0aa9bd7c2be9c094f58672bd5669a (patch)
tree19d57e6efdbe91ef1705f5be594942ab6513438f /arch/arm/boot/dts/omap44xx-clocks.dtsi
parentd809f2cca354d88ccc19aad1ecbe54704448615e (diff)
ARM: dts: omap44xx-clocks: Set IVA DPLL and its output clock rates
The IVA DPLL is not an essential DPLL for the functionality of a bootloader and is usually not configured (e.g. older u-boots configure it only if CONFIG_SYS_CLOCKS_ENABLE_ALL is enabled and u-boots newer than 2014.01 do not even have an option), and this results in incorrect operating frequencies when trying to use a DSP or IVAHD, whose root clocks are derived from this DPLL. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The reset values of the dividers M4 & M5 (functional clocks for DSP and IVAHD respectively) are identical to each other, but are different at each OPP. The reset values also do not match a specific OPP. So, the derived output clocks from the IVA DPLL have to be initialized as well to avoid initializing these divider outputs to incorrect frequencies. The clock rates are chosen based on the OPP100 values as defined in the OMAP4430 ES2.x Public TRM vAP, section "3.6.3.8.7 DPLL_IVA Preferred Settings". The DPLL locked frequency is 1862.4 MHz (value for DPLL_IVA_X2_CLK), so the dpll_iva_ck clock rate used is half of this value. Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/omap44xx-clocks.dtsi')
-rw-r--r--arch/arm/boot/dts/omap44xx-clocks.dtsi6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
index 9573b37fbaa7..9cb205b87835 100644
--- a/arch/arm/boot/dts/omap44xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -357,6 +357,8 @@
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+ assigned-clocks = <&dpll_iva_ck>;
+ assigned-clock-rates = <931200000>;
};
dpll_iva_x2_ck: dpll_iva_x2_ck {
@@ -374,6 +376,8 @@
reg = <0x01b8>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
+ assigned-clocks = <&dpll_iva_m4x2_ck>;
+ assigned-clock-rates = <465600000>;
};
dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc {
@@ -385,6 +389,8 @@
reg = <0x01bc>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
+ assigned-clocks = <&dpll_iva_m5x2_ck>;
+ assigned-clock-rates = <266100000>;
};
dpll_mpu_ck: dpll_mpu_ck@160 {