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authorSven Eckelmann <sven.eckelmann@openmesh.com>2017-04-28 12:10:36 +0200
committerAndy Gross <andy.gross@linaro.org>2017-06-05 21:22:09 -0500
commit5533b0cda3bf8b17e3688cce4b66bd5448d6cd1e (patch)
treea3fbdc0c46499b8c8693ce320a39dd0e3d6aa370 /arch/arm/boot/dts/qcom-ipq8064.dtsi
parentb993292f73dcffd113bd5196bd5898432ddd463d (diff)
ARM: dts: qcom: add gsbi7 serial to ipq8064 SoC device tree
The gsbi_serial7 under gsbi7 is used by the IPQ8068 based board EWS870AP as main serial console. Signed-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/qcom-ipq8064.dtsi')
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064.dtsi23
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 76f4e8921d58..f1fbffe59b93 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -284,6 +284,29 @@
};
};
+ gsbi7: gsbi@16600000 {
+ status = "disabled";
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <7>;
+ reg = <0x16600000 0x100>;
+ clocks = <&gcc GSBI7_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ syscon-tcsr = <&tcsr>;
+
+ gsbi7_serial: serial@16640000 {
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+ reg = <0x16640000 0x1000>,
+ <0x16600000 0x1000>;
+ interrupts = <0 158 0x0>;
+ clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+ };
+
sata_phy: sata-phy@1b400000 {
compatible = "qcom,ipq806x-sata-phy";
reg = <0x1b400000 0x200>;