diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-02-15 21:38:29 +0100 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-02-19 14:52:21 +0900 |
| commit | c86a4b621994dbe9361185362c4be6887f04b1a4 (patch) | |
| tree | 55dca258775d61ba8ae37f1d1fe33306839256f6 /arch/arm/boot/dts/r8a73a4.dtsi | |
| parent | 57f9156bc620ac561ed46b2316de328e6b280023 (diff) | |
ARM: dts: r8a73a4: Add L2 cache-controller nodes
Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.
The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways), and located in PM domain A3SM.
The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways), and located in PM domain A3KM.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a73a4.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a73a4.dtsi | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 138414a7d170..6583a1dfca1f 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -29,6 +29,7 @@ reg = <0>; clock-frequency = <1500000000>; power-domains = <&pd_a2sl>; + next-level-cache = <&L2_CA15>; }; }; @@ -45,6 +46,22 @@ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; + L2_CA15: cache-controller@0 { + compatible = "cache"; + clocks = <&cpg_clocks R8A73A4_CLK_Z>; + power-domains = <&pd_a3sm>; + cache-unified; + cache-level = <2>; + }; + + L2_CA7: cache-controller@1 { + compatible = "cache"; + clocks = <&cpg_clocks R8A73A4_CLK_Z2>; + power-domains = <&pd_a3km>; + cache-unified; + cache-level = <2>; + }; + dbsc1: memory-controller@e6790000 { compatible = "renesas,dbsc-r8a73a4"; reg = <0 0xe6790000 0 0x10000>; |