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authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>2017-04-20 21:51:35 +0300
committerSimon Horman <horms+renesas@verge.net.au>2017-07-27 16:28:32 +0200
commit51982d8f4722d1bbc2dabd79d4a1acebb90f6357 (patch)
tree0ce120f6ce9f288ee07fe4bf20a4f4898f0789e7 /arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
parent403812e4c4d853548237417fca2cf400351b72e6 (diff)
ARM: dts: sk-rzg1m: add Ether pins
Add the (previously omitted) Ether/PHY pin data to the SK-RZG1M board's device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7743-sk-rzg1m.dts')
-rw-r--r--arch/arm/boot/dts/r8a7743-sk-rzg1m.dts13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
index 97a066c22003..3d918d106593 100644
--- a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
+++ b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
@@ -44,6 +44,16 @@
groups = "scif0_data_d";
function = "scif0";
};
+
+ ether_pins: ether {
+ groups = "eth_link", "eth_mdio", "eth_rmii";
+ function = "eth";
+ };
+
+ phy1_pins: phy1 {
+ groups = "intc_irq0";
+ function = "intc";
+ };
};
&scif0 {
@@ -54,6 +64,9 @@
};
&ether {
+ pinctrl-0 = <&ether_pins &phy1_pins>;
+ pinctrl-names = "default";
+
phy-handle = <&phy1>;
renesas,ether-link-active-low;
status = "okay";