diff options
| author | Biju Das <biju.das@bp.renesas.com> | 2017-12-21 14:52:25 +0000 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-12-22 09:24:00 +0100 |
| commit | 5b062010675b3d74c9a6c6896e2becf932a4ca74 (patch) | |
| tree | 67f871a3e790ecf77c590b6d239fc05681b7e375 /arch/arm/boot/dts/r8a7745.dtsi | |
| parent | 6f41d5e0872e4b55a5352ff79ab2452bff306753 (diff) | |
ARM: dts: r8a7745: Add missing clock for secondary CA7 CPU core
Add the missing clock to CA7 CPU1 node.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7745.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7745.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 835a2821477b..ae918e9cce21 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -84,6 +84,7 @@ compatible = "arm,cortex-a7"; reg = <1>; clock-frequency = <1000000000>; + clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>; power-domains = <&sysc R8A7745_PD_CA7_CPU1>; next-level-cache = <&L2_CA7>; }; |