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authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>2014-11-03 17:47:46 -0800
committerSimon Horman <horms+renesas@verge.net.au>2014-11-19 09:21:44 +0900
commit177d8bea33899cef3989a2d0b4ea7213b5f34d0a (patch)
treed297a4a51321cc2988c3c7bb0e860fe05599b01c /arch/arm/boot/dts/r8a7790-lager.dts
parent40c6d9f0e7745012c9e19c955e22d4809104359c (diff)
ARM: shmobile: lager: fixup IIC2 clock frequency
Current Lager IIC2 is using default clock frequency, but, ak4643 audio codec chip needs 100kHz This patch clarifies IIC2 clock frequency as 100kHz. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7790-lager.dts')
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 830f2e87df49..86fb2ee29782 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -429,6 +429,8 @@
pinctrl-0 = <&iic2_pins>;
pinctrl-names = "default";
+ clock-frequency = <100000>;
+
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;