diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-01-29 11:17:22 +0100 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-02-09 19:43:26 +0100 |
| commit | 1781460c9accb106b0887985754b63be1b4c63f8 (patch) | |
| tree | e90ed57204b638b043b3c91a36bc7fccbfe308a2 /arch/arm/boot/dts/r8a7790-lager.dts | |
| parent | 338f7ebf46e184746e63bcb93b3e5dbee95564a3 (diff) | |
ARM: dts: lager: Enable SCIF_CLK frequency and pins
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.
This increases the range and accuracy of supported baud rates.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7790-lager.dts')
| -rw-r--r-- | arch/arm/boot/dts/r8a7790-lager.dts | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 052dcee4790d..cdc0414f5f07 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -291,6 +291,9 @@ }; &pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + du_pins: du { renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0"; renesas,function = "du"; @@ -301,6 +304,11 @@ renesas,function = "scif0"; }; + scif_clk_pins: scif_clk { + renesas,groups = "scif_clk"; + renesas,function = "scif_clk"; + }; + ether_pins: ether { renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; renesas,function = "eth"; @@ -485,6 +493,11 @@ status = "okay"; }; +&scif_clk { + clock-frequency = <14745600>; + status = "okay"; +}; + &msiof1 { pinctrl-0 = <&msiof1_pins>; pinctrl-names = "default"; |