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authorWolfram Sang <wsa+renesas@sang-engineering.com>2014-07-10 12:50:56 +0200
committerSimon Horman <horms+renesas@verge.net.au>2014-07-11 10:47:06 +0200
commitcb9a2b12e0cb524022c9a81d8ed29f2453ec240d (patch)
treed0a4db28390b29db6afe918e000cc92de3d5bc6a /arch/arm/boot/dts/r8a7790-lager.dts
parent5179ffd099446e65a1e094b9cb17cc7edab45583 (diff)
ARM: shmobile: r8a7790: lager: use iic cores instead of i2c
On Lager board, i2c and iic cores can be interchanged since they can be muxed to the same wires. Commit e489c2a9bc82713167d9f721ca764f4b0d37e543 ("ARM: shmobile: lager: enable i2c devices") activated the i2c cores, yet the iic cores should be default since they have the more interesting features for generic use cases, i.e. SMBUS_QUICK and DMA (yet to be supported). Reported-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7790-lager.dts')
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts22
1 files changed, 11 insertions, 11 deletions
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index ffe0523ff16f..856b4236b674 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -205,14 +205,14 @@
renesas,function = "msiof1";
};
- i2c1_pins: i2c1 {
- renesas,groups = "i2c1";
- renesas,function = "i2c1";
+ iic1_pins: iic1 {
+ renesas,groups = "iic1";
+ renesas,function = "iic1";
};
- i2c2_pins: i2c2 {
- renesas,groups = "i2c2";
- renesas,function = "i2c2";
+ iic2_pins: iic2 {
+ renesas,groups = "iic2";
+ renesas,function = "iic2";
};
iic3_pins: iic3 {
@@ -352,19 +352,19 @@
cpu0-supply = <&vdd_dvfs>;
};
-&i2c0 {
+&iic0 {
status = "ok";
};
-&i2c1 {
+&iic1 {
status = "ok";
- pinctrl-0 = <&i2c1_pins>;
+ pinctrl-0 = <&iic1_pins>;
pinctrl-names = "default";
};
-&i2c2 {
+&iic2 {
status = "ok";
- pinctrl-0 = <&i2c2_pins>;
+ pinctrl-0 = <&iic2_pins>;
pinctrl-names = "default";
};