diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-10-12 11:35:12 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-10-16 11:41:41 +0200 |
| commit | 60b672fe7e28358c1cffdab4724b203f6cf2901b (patch) | |
| tree | 248fc0a7fab2d268b6dec74dc70d67039349530a /arch/arm/boot/dts/r8a7791.dtsi | |
| parent | aea0089ae8058a9bf4c9766f3208809fc28c99f0 (diff) | |
ARM: dts: r8a7791: Add missing clock for secondary CA15 CPU core
Currently only the primary CPU in the CA15 cluster has a clocks
property, while the secondary CPU core is driven by the same clock.
Add the missing clocks property to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7791.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7791.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 3c7b919efa48..67831d0405f3 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -70,6 +70,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; power-domains = <&sysc R8A7791_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; }; |