diff options
| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2015-01-06 01:24:08 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2015-02-24 06:30:55 +0900 |
| commit | b324252cc18d52d5752942a8574c22229153c58f (patch) | |
| tree | 21f580868c9421e8d8145ffb1786400e1c3bd0b6 /arch/arm/boot/dts/r8a7791.dtsi | |
| parent | 6a7742b4eea5de4af68bb62c20ca56e38b8e5b8b (diff) | |
ARM: shmobile: r8a7791: add CAN clocks
The R-Car CAN controllers can derive the CAN bus clock not only from their
peripheral clock input (clkp1) but also from the other internal clock (clkp2)
and external clock fed on CAN_CLK pin. Describe those clocks in the device
tree, along with the USB_EXTAL clock from which clkp2 is derived.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7791.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7791.dtsi | 23 |
1 files changed, 21 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index afba8af1a5e4..1ebffef5b908 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -862,15 +862,34 @@ status = "disabled"; }; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "usb_extal"; + }; + + /* External CAN clock */ + can_clk: can_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + clock-output-names = "can_clk"; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7791-cpg-clocks", "renesas,rcar-gen2-cpg-clocks"; reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; + clocks = <&extal_clk &usb_extal_clk>; #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "z"; + "lb", "qspi", "sdh", "sd0", "z", + "rcan"; }; /* Variable factor clocks */ |