diff options
| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2016-07-15 00:00:56 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-08-08 12:52:48 +0200 |
| commit | 2cd452d19e6e79ea58c8022c43248b64d579db60 (patch) | |
| tree | 22a50e0120b230262afc6bb861a68697294b28ea /arch/arm/boot/dts/r8a7792-blanche.dts | |
| parent | 02183a5250193aae6913ed3ee720be021ae92b03 (diff) | |
ARM: dts: blanche: add SCIF0/3 pins
Add the (previously omitted) SCIF0/3 pin data to the Blanche board's
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7792-blanche.dts')
| -rw-r--r-- | arch/arm/boot/dts/r8a7792-blanche.dts | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index e7b40f0e7da6..9b550bde939a 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -57,10 +57,28 @@ clock-frequency = <20000000>; }; +&pfc { + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; + + scif3_pins: scif3 { + groups = "scif3_data"; + function = "scif3"; + }; +}; + &scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; }; &scif3 { + pinctrl-0 = <&scif3_pins>; + pinctrl-names = "default"; + status = "okay"; }; |