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authorMagnus Damm <damm+renesas@opensource.se>2016-06-28 16:10:42 +0200
committerSimon Horman <horms+renesas@verge.net.au>2016-06-29 14:30:30 +0200
commit65b133cd79cfde9f4e0157deb0e0f88f92811ad3 (patch)
treeb235aa92a978fbc9a3cdbb537bfaa16c96e3c413 /arch/arm/boot/dts/r8a7793.dtsi
parent477cbcbd8f089ab72721a90760bc5d7987d3a713 (diff)
ARM: dts: r8a7793: Add APMU node and second CPU core
Add DT nodes for the Advanced Power Management Unit (APMU) and the second CPU core. Use the enable-method to point out that the APMU should be used for SMP support. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7793.dtsi')
-rw-r--r--arch/arm/boot/dts/r8a7793.dtsi15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 9b55c1c6ee31..8d02aacf2892 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -35,6 +35,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -56,6 +57,14 @@
next-level-cache = <&L2_CA15>;
};
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <1500000000>;
+ power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
+ };
+
L2_CA15: cache-controller@0 {
compatible = "cache";
reg = <0>;
@@ -65,6 +74,12 @@
};
};
+ apmu@e6152000 {
+ compatible = "renesas,r8a7793-apmu", "renesas,apmu";
+ reg = <0 0xe6152000 0 0x188>;
+ cpus = <&cpu0 &cpu1>;
+ };
+
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <0>;