diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-03-06 17:40:43 +0100 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-03-07 07:45:40 +0100 |
| commit | 65d0b7ed40f8a3a41a0ac5ed5ca4d1874c6aaf2d (patch) | |
| tree | 6a03a56df59eb7a6189d32b9ca9837ba3143277b /arch/arm/boot/dts/r8a7794.dtsi | |
| parent | beffa8872a3680ef804eb0320ec77037170f4686 (diff) | |
ARM: dts: r8a7794: Remove unit-address and reg from integrated cache
The Cortex-A7 cache controller is an integrated controller, and thus the
device node representing it should not have a unit-addresses or reg
property.
Fixes: 34ea4b4a827b4ee7 ("ARM: dts: r8a7794: Fix W=1 dtc warnings")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7794.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7794.dtsi | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 319c1069b7ee..cb31cd2232f9 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -56,9 +56,8 @@ next-level-cache = <&L2_CA7>; }; - L2_CA7: cache-controller@0 { + L2_CA7: cache-controller-0 { compatible = "cache"; - reg = <0>; power-domains = <&sysc R8A7794_PD_CA7_SCU>; cache-unified; cache-level = <2>; |