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authorDouglas Anderson <dianders@chromium.org>2019-04-11 16:21:55 -0700
committerHeiko Stuebner <heiko@sntech.de>2019-04-12 13:14:29 +0200
commit8a5deb4e316a5469f137e62eb1bbf6147ddbfd3d (patch)
tree0f9d0ae62cf8db773c75924d0285c4ee8e4815ad /arch/arm/boot/dts/rk3288-veyron.dtsi
parentac60c5e33df4ec2b69c7e3ebbc0ccf1557e7bd5e (diff)
ARM: dts: rockchip: Add DDR retention/poweroff to rk3288-veyron hogs
Even though upstream Linux doesn't yet go into deep enough suspend to get DDR into self refresh, there is no harm in setting these pins up. They'll only actually do something if we go into a deeper suspend but leaving them configed always is fine. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3288-veyron.dtsi')
-rw-r--r--arch/arm/boot/dts/rk3288-veyron.dtsi4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
index e4f0c00011f2..35755870bf66 100644
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -453,10 +453,14 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
&global_pwroff
>;
pinctrl-1 = <
/* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
&global_pwroff
>;