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authorMatthias Kaehlcke <mka@chromium.org>2019-07-31 08:15:27 -0700
committerHeiko Stuebner <heiko@sntech.de>2019-08-03 00:33:45 +0200
commit94562040da08611ca15eecb39c68be8caac4bf06 (patch)
tree51c8197c190865088d37d8558fb63c5e1bc2ca3e /arch/arm/boot/dts/rk3288-veyron.dtsi
parenta5021c4597913aad16d9d176cbd1de7fa514477e (diff)
ARM: dts: rockchip: A few fixes for veyron-{fievel,tiger}
Fix/improve a few things for veyron fievel/tiger: - move 'vccsys' regulator from tiger to fievel, both boards have it (and tiger includes the fievel .dtsi) - move 'ext_gmac' node below regulators - fix GPIO ids of vcc5_host1 and vcc5_host2 regulators - remove reset configuration from 'gmac' node, this is already done in rk3288.dtsi - fixed style issues of some multi-line comments - switch 'vcc18_lcdt', 'vdd10_lcd' and 'vcc33_ccd' regulators off during suspend - no pull-up on the Bluetooth wake-up pin, there is an external pull-up. The signal is active low, add the 'bt_host_wake_l' pinctrl config - move BC 1.2 pins up in the pinctrl config to keep 'wake only' pins separate - add BC 1.2 pins to sleep config Fixes: 0067692b662e ("ARM: dts: rockchip: add veyron-fievel board") Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3288-veyron.dtsi')
-rw-r--r--arch/arm/boot/dts/rk3288-veyron.dtsi4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
index 8fc8eac699bf..7525e3dd1fc1 100644
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -586,6 +586,10 @@
rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>;
};
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
/*
* We run sdio0 at max speed; bump up drive strength.
* We also have external pulls, so disable the internal ones.