diff options
| author | Caesar Wang <caesar.wang@rock-chips.com> | 2019-04-09 13:47:07 -0700 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2019-05-20 01:00:20 +0200 |
| commit | 6773af2684b7bc1b7b2d9ef874599cccaba2559e (patch) | |
| tree | 99ea800062913fdd53d8122cf1b5118fff36e7ac /arch/arm/boot/dts/rk3288.dtsi | |
| parent | a188339ca5a396acc588e5851ed7e19f66b0ebd9 (diff) | |
ARM: dts: rockchip: fix PWM clock found on RK3288 Socs
We use the new PWM IP on RK3288, but the PWM's clock indeed incorrect.
Signed-off-by: Caesar Wang <caesar.wang@rock-chips.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3288.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/rk3288.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index aa017abf4f42..171231a0cd9b 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -682,7 +682,7 @@ #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&pwm0_pin>; - clocks = <&cru PCLK_PWM>; + clocks = <&cru PCLK_RKPWM>; clock-names = "pwm"; status = "disabled"; }; @@ -693,7 +693,7 @@ #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&pwm1_pin>; - clocks = <&cru PCLK_PWM>; + clocks = <&cru PCLK_RKPWM>; clock-names = "pwm"; status = "disabled"; }; @@ -704,7 +704,7 @@ #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&pwm2_pin>; - clocks = <&cru PCLK_PWM>; + clocks = <&cru PCLK_RKPWM>; clock-names = "pwm"; status = "disabled"; }; @@ -715,7 +715,7 @@ #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pwm3_pin>; - clocks = <&cru PCLK_PWM>; + clocks = <&cru PCLK_RKPWM>; clock-names = "pwm"; status = "disabled"; }; |