diff options
| author | Thor Thayer <tthayer@opensource.altera.com> | 2016-03-21 16:01:46 +0000 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2016-04-11 14:03:08 -0500 |
| commit | 64ded09d293932621aad94dddf6d14eb0690246a (patch) | |
| tree | 51870ab79ef8acd25aacaf2f97438d594af66752 /arch/arm/boot/dts/socfpga_arria10.dtsi | |
| parent | 95c16caaa8c1ffff2b58007da3989d7c470069eb (diff) | |
ARM: dts: socfpga: Add Altera Arria10 L2 Cache EDAC devicetree entry
Add the device tree entries needed to support the Altera L2
cache EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'arch/arm/boot/dts/socfpga_arria10.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/socfpga_arria10.dtsi | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 8d102d310212..04da5eac8376 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -603,6 +603,21 @@ reg = <0xffe00000 0x40000>; }; + eccmgr: eccmgr@ffd06000 { + compatible = "altr,socfpga-a10-ecc-manager"; + altr,sysmgr-syscon = <&sysmgr>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 0 IRQ_TYPE_LEVEL_HIGH>; + ranges; + + l2-ecc@ffd06010 { + compatible = "altr,socfpga-a10-l2-ecc"; + reg = <0xffd06010 0x4>; + }; + }; + rst: rstmgr@ffd05000 { #reset-cells = <1>; compatible = "altr,rst-mgr"; |