diff options
| author | Dinh Nguyen <dinguyen@opensource.altera.com> | 2016-01-05 14:59:38 -0600 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2016-04-11 13:47:22 -0500 |
| commit | faf68cdfdf6c9f0999686802ad066b1378b89413 (patch) | |
| tree | e2bbd8f97d29c3bf1c1e5955277f963c3cb52183 /arch/arm/boot/dts/socfpga_arria10.dtsi | |
| parent | d07e187cf0621891514a47f316597fea8963e5a7 (diff) | |
ARM: dts: socfpga: add the clk-phase property for sd/mmc clock
The CIU clock for the SD/MMC should be the sdmmc_clk and not the
sdmmc_free_clk. Also, add the correct phase shift the sdmmc_clk.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'arch/arm/boot/dts/socfpga_arria10.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/socfpga_arria10.dtsi | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 1c5e139e4d05..f75dd232ec2e 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -362,6 +362,7 @@ compatible = "altr,socfpga-a10-gate-clk"; clocks = <&sdmmc_free_clk>; clk-gate = <0xC8 5>; + clk-phase = <0 135>; }; qspi_clk: qspi_clk { @@ -589,7 +590,7 @@ reg = <0xff808000 0x1000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; fifo-depth = <0x400>; - clocks = <&l4_mp_clk>, <&sdmmc_free_clk>; + clocks = <&l4_mp_clk>, <&sdmmc_clk>; clock-names = "biu", "ciu"; status = "disabled"; }; |