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| author | Dinh Nguyen <dinguyen@opensource.altera.com> | 2015-07-16 15:48:50 -0500 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@opensource.altera.com> | 2015-07-20 10:06:11 -0500 |
| commit | 2211a658620a35f3b3eabdfa2587f46b7abf3ee7 (patch) | |
| tree | ba16bcf653a706bdcfda2f9087391da6acd68aba /arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | |
| parent | d770e558e21961ad6cfdf0ff7df0eb5d7d4f0754 (diff) | |
ARM: dts: socfpga: enable the data and instruction prefetch for the l2 cache
Just in case the firmware did not enable data and instruction prefetch in
the L2 cache controller, we enable it in the kernel.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'arch/arm/boot/dts/socfpga_cyclone5_sockit.dts')
0 files changed, 0 insertions, 0 deletions