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authorDinh Nguyen <dinguyen@opensource.altera.com>2016-10-19 14:55:54 -0500
committerDinh Nguyen <dinguyen@kernel.org>2016-11-08 15:40:35 -0600
commit466e90ca2138c92b1e47d919237488b445b44d73 (patch)
tree82b1e21669e54ae5a669edfa75e366d6de4d059a /arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
parent1df99da8953afd4aef75f2dee77b61fc07e918e1 (diff)
ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit
Enable the QSPI node and add the flash chip. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v3: Use n25q00 for the compatible entry for the flash part and tested on SoCKit v2: Remove partition entries for the SoCKIT
Diffstat (limited to 'arch/arm/boot/dts/socfpga_cyclone5_sockit.dts')
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_sockit.dts21
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
index fcacaf7b2c83..a0c90b3bdfd1 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
@@ -175,6 +175,27 @@
status = "okay";
};
+&qspi {
+ status = "okay";
+
+ flash: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+
+ m25p,fast-read;
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ };
+};
+
&usb1 {
status = "okay";
};