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authorLinus Walleij <linus.walleij@linaro.org>2014-02-03 22:43:45 +0100
committerLinus Walleij <linus.walleij@linaro.org>2014-02-04 20:50:36 +0100
commitc7bb47aa0145ccb5e725f79cc7775d1093467467 (patch)
tree727eaf20831a02abe6fc1abdf29c90409194ddeb /arch/arm/boot/dts/ste-href-ab8500.dtsi
parentb2985cf7f08325519405942770d203da8fd46fa8 (diff)
ARM: ux500: move AB8500 USB UICC settings to DT
This moves the set-up of the USB UICC (InteChip USB) from the board file to the device tree. Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/ste-href-ab8500.dtsi')
-rw-r--r--arch/arm/boot/dts/ste-href-ab8500.dtsi19
1 files changed, 18 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
index 3aae4ec5bcc9..9cf12d5d0923 100644
--- a/arch/arm/boot/dts/ste-href-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -34,7 +34,8 @@
<&gpio35_default_mode>,
<&ycbcr_default_mode>,
<&pwm_default_mode>,
- <&adi1_default_mode>;
+ <&adi1_default_mode>,
+ <&usbuicc_default_mode>;
/*
* Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42
@@ -301,6 +302,22 @@
};
};
};
+ /* This sets up the USB UICC pins */
+ usbuicc {
+ usbuicc_default_mode: usbuicc_default {
+ default_mux {
+ ste,function = "usbuicc";
+ ste,pins = "usbuicc_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO21_H19",
+ "GPIO22_G20",
+ "GPIO23_G19";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
};
};
};