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authorLinus Walleij <linus.walleij@linaro.org>2013-01-05 00:29:31 +0100
committerLinus Walleij <linus.walleij@linaro.org>2013-01-28 23:23:44 +0100
commitf8635abd38776a413d1e84c79353693b8ecf45c9 (patch)
tree335410b72facf10dac9bbd53aeafd570eb4dd538 /arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
parenta352d85adbe8ed0c5c8c69e3ea0ee1833b3ee27e (diff)
ARM: nomadik: initial devicetree support
Support basic device tree boot on the Nomadik. Implement the support in the cpu file with the intent of deleting the board files later. At this stage IRQ controllers, system timer, l2x0 cache, UARTs and thus console boot is fully functional. Patch out the code adding devices by initcalls for now so as not to disturb the boot. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/ste-nomadik-stn8815.dtsi')
-rw-r--r--arch/arm/boot/dts/ste-nomadik-stn8815.dtsi80
1 files changed, 80 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
new file mode 100644
index 000000000000..0a5b670430de
--- /dev/null
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -0,0 +1,80 @@
+/*
+ * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC
+ */
+/include/ "skeleton.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memory {
+ reg = <0x00000000 0x04000000>,
+ <0x08000000 0x04000000>;
+ };
+
+ L2: l2-cache {
+ compatible = "arm,l210-cache";
+ reg = <0x10210000 0x1000>;
+ interrupt-parent = <&vica>;
+ interrupts = <30>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ mtu0 {
+ /* Nomadik system timer */
+ reg = <0x101e2000 0x1000>;
+ interrupt-parent = <&vica>;
+ interrupts = <4>;
+ };
+
+ mtu1 {
+ /* Secondary timer */
+ reg = <0x101e3000 0x1000>;
+ interrupt-parent = <&vica>;
+ interrupts = <5>;
+ };
+
+ amba {
+ compatible = "arm,amba-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ vica: intc@0x10140000 {
+ compatible = "arm,versatile-vic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x10140000 0x20>;
+ };
+
+ vicb: intc@0x10140020 {
+ compatible = "arm,versatile-vic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x10140020 0x20>;
+ };
+
+ uart0: uart@101fd000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x101fd000 0x1000>;
+ interrupt-parent = <&vica>;
+ interrupts = <12>;
+ };
+
+ uart1: uart@101fb000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x101fb000 0x1000>;
+ interrupt-parent = <&vica>;
+ interrupts = <17>;
+ };
+
+ uart2: uart@101f2000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x101f2000 0x1000>;
+ interrupt-parent = <&vica>;
+ interrupts = <28>;
+ status = "disabled";
+ };
+ };
+};