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authorLinus Walleij <linus.walleij@linaro.org>2013-11-17 11:13:21 +0100
committerLinus Walleij <linus.walleij@linaro.org>2013-11-26 21:01:57 +0100
commitfd8f9eac9dca386f54dfeff94afd03c84ec72ca1 (patch)
tree1b92cf52f0c88f0ed4af58c9f885e2c15fc8e192 /arch/arm/boot/dts/ste-snowball.dts
parenta48bf4b9fcf63a43e10f3c784d7349bb868ccc45 (diff)
ARM: ux500: convert Snowball SPI pin reference
The SPI0 block is not at all connected to the AB8500 on the Snowball: it is connected to the external header. These pins on the header may also be used for GPIO, but let's assume that SPI is a probable usecase on the Snowball and mux in the SPI block and use these for SPI. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/ste-snowball.dts')
-rw-r--r--arch/arm/boot/dts/ste-snowball.dts28
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index 4f5457a91589..744ab956059a 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -248,6 +248,11 @@
pinctrl-1 = <&i2c3_sleep_mode>;
};
+ ssp@80002000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ssp0_snowball_mode>;
+ };
+
cpufreq-cooling {
status = "okay";
};
@@ -386,6 +391,29 @@
};
};
+ ssp0 {
+ ssp0_snowball_mode: ssp0_snowball_default {
+ snowball_mux {
+ ste,function = "ssp0";
+ ste,pins = "ssp0_a_1";
+ };
+ snowball_cfg1 {
+ ste,pins = "GPIO144_B13"; /* FRM */
+ ste,config = <&gpio_out_hi>;
+ };
+ snowball_cfg2 {
+ ste,pins = "GPIO145_C13"; /* RXD */
+ ste,config = <&in_pd>;
+ };
+ snowball_cfg3 {
+ ste,pins =
+ "GPIO146_D13", /* TXD */
+ "GPIO143_D12"; /* CLK */
+ ste,config = <&out_lo>;
+ };
+
+ };
+ };
};
mcde@a0350000 {