diff options
| author | Peter Griffin <peter.griffin@linaro.org> | 2015-06-10 16:04:00 +0200 |
|---|---|---|
| committer | Maxime Coquelin <maxime.coquelin@st.com> | 2015-07-22 11:03:11 +0200 |
| commit | 810099f657579058b17fba28a0ce1414771f4d92 (patch) | |
| tree | 8fe3538c7c708ec455f37cf0f29f16f0c56df2dc /arch/arm/boot/dts/stih407-pinctrl.dtsi | |
| parent | e0decdd60a730fe9d5607403ef48a4548d25ff24 (diff) | |
ARM: STi: DT: Add STiH407 family mtsin0 pinctrl configuration
mtsin0 channel can only be configured for parallel data transfer.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Diffstat (limited to 'arch/arm/boot/dts/stih407-pinctrl.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/stih407-pinctrl.dtsi | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index b52cf4070e53..1683debd0854 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -608,6 +608,25 @@ }; }; }; + + mtsin0 { + pinctrl_mtsin0_parallel: mtsin0_parallel { + st,pins { + DATA7 = <&pio10 4 ALT3 IN SE_NICLK_IO 0 CLK_A>; + DATA6 = <&pio10 5 ALT3 IN SE_NICLK_IO 0 CLK_A>; + DATA5 = <&pio10 6 ALT3 IN SE_NICLK_IO 0 CLK_A>; + DATA4 = <&pio10 7 ALT3 IN SE_NICLK_IO 0 CLK_A>; + DATA3 = <&pio11 0 ALT3 IN SE_NICLK_IO 0 CLK_A>; + DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>; + DATA1 = <&pio11 2 ALT3 IN SE_NICLK_IO 0 CLK_A>; + DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio10 3 ALT3 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio10 1 ALT3 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio10 0 ALT3 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio10 2 ALT3 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; }; pin-controller-front1 { |