diff options
| author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-03-23 17:38:31 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-04-19 12:02:21 +0200 |
| commit | 541ac1554e1269c4462a2166992d87b752abda64 (patch) | |
| tree | 898a55c85ad595ec0def7d526aaae45b35840b70 /arch/arm/boot/dts/sun5i-a13.dtsi | |
| parent | 15bd920f9670f7fe13cec9148e5c05d160c2f30c (diff) | |
ARM: sun5i: Add DRAM gates
The DRAM gates control whether the image / display devices on the SoC have
access to the DRAM clock or not.
Enable it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun5i-a13.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sun5i-a13.dtsi | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index 7bbeec9fae92..39f23b1ebc8f 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -61,7 +61,8 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; - clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>; + clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, + <&dram_gates 26>; status = "disabled"; }; }; @@ -149,6 +150,26 @@ "apb1_i2c2", "apb1_uart1", "apb1_uart3"; }; + + dram_gates: clk@01c20100 { + #clock-cells = <1>; + compatible = "allwinner,sun5i-a13-dram-gates-clk", + "allwinner,sun4i-a10-gates-clk"; + reg = <0x01c20100 0x4>; + clocks = <&pll5 0>; + clock-indices = <0>, + <1>, + <25>, + <26>, + <29>, + <31>; + clock-output-names = "dram_ve", + "dram_csi", + "dram_de_fe", + "dram_de_be", + "dram_ace", + "dram_iep"; + }; }; soc@01c00000 { |