diff options
| author | Boris BREZILLON <boris.brezillon@free-electrons.com> | 2014-05-13 16:03:03 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2014-05-15 10:38:00 +0200 |
| commit | 209394aed532c5de9bf549f4beac92bf1b80f887 (patch) | |
| tree | 5ba4c37b9bf01181547478df53de00e4e29162da /arch/arm/boot/dts/sun6i-a31.dtsi | |
| parent | cc08f5e9c10fba240687561590c7c5286679a052 (diff) | |
ARM: sunxi: dt: declare the r_pio pin controller for A31 SoC
The A31 SoC has a different pin controller for PL and PM banks.
Define this new controller in the device tree.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun6i-a31.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sun6i-a31.dtsi | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 90398fa1d0e5..2ad880c0821d 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -734,5 +734,19 @@ compatible = "allwinner,sun6i-a31-cpuconfig"; reg = <0x01f01c00 0x300>; }; + + r_pio: pinctrl@01f02c00 { + compatible = "allwinner,sun6i-a31-r-pinctrl"; + reg = <0x01f02c00 0x400>; + interrupts = <0 45 4>, + <0 46 4>; + clocks = <&apb0_gates 0>; + resets = <&apb0_rst 0>; + gpio-controller; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #gpio-cells = <3>; + }; }; }; |