summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/sun6i-a31.dtsi
diff options
context:
space:
mode:
authorChen-Yu Tsai <wens@csie.org>2014-07-16 01:15:45 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2014-07-18 22:36:49 +0200
commit3dca65f8a67c525cbddfb1fca149435ab4ce37b0 (patch)
treea8998d471b60d39aee3befaa89ea9c5787554ade /arch/arm/boot/dts/sun6i-a31.dtsi
parented29861ae87953e0d559baaf9d225e8f8a8ff19a (diff)
ARM: dts: sun6i: Add A31 GMAC gigabit ethernet controller node
The A31 has the same GMAC found on the A20 SoC, except it has an extra reset control. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun6i-a31.dtsi')
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi17
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index b78a5aa4bccc..578fde202cc1 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -691,6 +691,23 @@
status = "disabled";
};
+ gmac: ethernet@01c30000 {
+ compatible = "allwinner,sun7i-a20-gmac";
+ reg = <0x01c30000 0x1054>;
+ interrupts = <0 82 4>;
+ interrupt-names = "macirq";
+ clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
+ clock-names = "stmmaceth", "allwinner_gmac_tx";
+ resets = <&ahb1_rst 17>;
+ reset-names = "stmmaceth";
+ snps,pbl = <2>;
+ snps,fixed-burst;
+ snps,force_sf_dma_mode;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
timer@01c60000 {
compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
reg = <0x01c60000 0x1000>;