diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2016-01-21 13:26:36 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-01-25 00:01:21 +0100 |
| commit | 9fc1db1b7e4d9fc254968b1e0340732a60fba0a6 (patch) | |
| tree | 267112e71cd441db3de31dcf84b9e1466f849aea /arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | |
| parent | a22f8b22a9496396d7a8512225dace208645e04c (diff) | |
ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC
According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal
voltage sensing, and "cap-mmc-hw-reset" to denote this instance can use
eMMC hardware reset.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi index ea69fb8ad4d8..4ec0c8679b2e 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi @@ -61,12 +61,14 @@ }; /* eMMC on core board */ -&mmc2 { +&mmc3 { pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_emmc_pins>; + pinctrl-0 = <&mmc3_8bit_emmc_pins>; vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; bus-width = <8>; non-removable; + cap-mmc-hw-reset; status = "okay"; }; |