diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2015-12-05 21:16:46 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2015-12-07 10:21:26 +0100 |
| commit | 0b4bf5a5200b9ac5ddf545665f171feb5594677d (patch) | |
| tree | e58ddb0105a08bf0f2ddf6c4e2a77577eae42146 /arch/arm/boot/dts/sun7i-a20.dtsi | |
| parent | 82f8582feef4c048ee7ef0155a71c23614a7856d (diff) | |
ARM: dts: sun7i: Add DRAM gates
The DRAM gates controls direct memory access for some peripherals.
These peripherals include the display pipeline, so add the required
gates to the simplefb nodes as well.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sun7i-a20.dtsi | 32 |
1 files changed, 29 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index e02eb720c4fc..21169c0a6627 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -68,7 +68,7 @@ "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>; + <&ahb_gates 44>, <&dram_gates 26>; status = "disabled"; }; @@ -76,7 +76,8 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; - clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>; + clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, + <&dram_gates 26>; status = "disabled"; }; @@ -85,7 +86,7 @@ "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-tve0"; clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, - <&ahb_gates 44>; + <&ahb_gates 44>, <&dram_gates 26>; status = "disabled"; }; }; @@ -501,6 +502,31 @@ clock-output-names = "spi3"; }; + dram_gates: clk@01c20100 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-dram-gates-clk"; + reg = <0x01c20100 0x4>; + clocks = <&pll5 0>; + clock-indices = <0>, + <1>, <2>, + <3>, + <4>, + <5>, <6>, + <15>, + <24>, <25>, + <26>, <27>, + <28>, <29>; + clock-output-names = "dram_ve", + "dram_csi0", "dram_csi1", + "dram_ts", + "dram_tvd", + "dram_tve0", "dram_tve1", + "dram_output", + "dram_de_fe1", "dram_de_fe0", + "dram_de_be0", "dram_de_be1", + "dram_de_mp", "dram_ace"; + }; + codec_clk: clk@01c20140 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-codec-clk"; |