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authorChen-Yu Tsai <wens@csie.org>2018-01-17 16:46:50 +0800
committerChen-Yu Tsai <wens@csie.org>2018-02-16 12:19:14 +0800
commitfd4b0c334040bb39087454d700155e5f25227ead (patch)
tree286ab836a975d5443d256f36ed6c9924941326f9 /arch/arm/boot/dts/sun9i-a80.dtsi
parent61cf3ed092c68c9652271320b3808ecf4f5ed12f (diff)
ARM: dts: sun9i: Add PRCM device node for the A80 dtsi
The PRCM is a collection of clock controls, reset controls, and various power switches/gates. Some of these can be independently listed and supported, while a number of CPU related ones are used in tandem with CPUCFG for SMP bringup and CPU hotplugging. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'arch/arm/boot/dts/sun9i-a80.dtsi')
-rw-r--r--arch/arm/boot/dts/sun9i-a80.dtsi5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 85ecb4d64cfd..bf4d40e8359f 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -709,6 +709,11 @@
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
};
+ prcm@8001400 {
+ compatible = "allwinner,sun9i-a80-prcm";
+ reg = <0x08001400 0x200>;
+ };
+
apbs_rst: reset@80014b0 {
reg = <0x080014b0 0x4>;
compatible = "allwinner,sun6i-a31-clock-reset";