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authorLaxman Dewangan <ldewangan@nvidia.com>2014-02-23 12:16:48 +0530
committerLaxman Dewangan <ldewangan@nvidia.com>2014-02-26 06:08:37 -0800
commitcd916e855bf3738119a475abca2fd7b197707f41 (patch)
tree2040b61eafed20513a43407c007754e1c4aeb53c /arch/arm/boot/dts/tegra124-platforms/tegra124-loki-powermon-e2548.dtsi
parent203b785c476295386d469b75ed3777579b33c340 (diff)
ARM: tegra: move powermon to DT for Loki
Move all power monitor device registration for Loki to DT. Following are change: - Add dtsi file for Loki power mon. - Add the dtsi file from the Loki top level dtsi file. - Delete the board powermon dts file. bug 1369958 Change-Id: Ideae40a193f2260834ce25dbd48a43c6e5bc0c6e Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/374140
Diffstat (limited to 'arch/arm/boot/dts/tegra124-platforms/tegra124-loki-powermon-e2548.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra124-platforms/tegra124-loki-powermon-e2548.dtsi86
1 files changed, 86 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra124-platforms/tegra124-loki-powermon-e2548.dtsi b/arch/arm/boot/dts/tegra124-platforms/tegra124-loki-powermon-e2548.dtsi
new file mode 100644
index 000000000000..680660a988a8
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-platforms/tegra124-loki-powermon-e2548.dtsi
@@ -0,0 +1,86 @@
+/ {
+ i2c@7000c400 {
+ ina3221x@40 {
+ compatible = "ti,ina3221x";
+ reg = <0x40>;
+ ti,trigger-config = <0x7003>;
+ ti,continuous-config = <0x7727>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0x0>;
+ ti,rail-name = "VDD_CPU";
+ ti,shunt-resistor-mohm = <5>;
+ };
+
+ channel@1 {
+ reg = <0x1>;
+ ti,rail-name = "VDD_BAT";
+ ti,shunt-resistor-mohm = <5>;
+ ti,current-critical-limit-ma = <6800>;
+ };
+
+ channel@2 {
+ reg = <0x2>;
+ ti,rail-name = "VDD_VBUS";
+ ti,shunt-resistor-mohm = <20>;
+ };
+ };
+
+ ina3221x@41 {
+ compatible = "ti,ina3221x";
+ reg = <0x41>;
+ ti,trigger-config = <0x7003>;
+ ti,continuous-config = <0x7727>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0x0>;
+ ti,rail-name = "VDD_DDR";
+ ti,shunt-resistor-mohm = <30>;
+ };
+
+ channel@1 {
+ reg = <0x1>;
+ ti,rail-name = "VDD_SOC";
+ ti,shunt-resistor-mohm = <30>;
+ };
+
+ channel@2 {
+ reg = <0x2>;
+ ti,rail-name = "VDD_GPU";
+ ti,shunt-resistor-mohm = <10>;
+ };
+ };
+
+ ina3221x@42 {
+ compatible = "ti,ina3221x";
+ reg = <0x42>;
+ ti,trigger-config = <0x7003>;
+ ti,continuous-config = <0x7727>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0x0>;
+ ti,rail-name = "VDD_3V3_SYS";
+ ti,shunt-resistor-mohm = <30>;
+ };
+
+ channel@1 {
+ reg = <0x1>;
+ ti,rail-name = "VDD_EMMC";
+ ti,shunt-resistor-mohm = <30>;
+ };
+
+ channel@2 {
+ reg = <0x2>;
+ ti,rail-name = "VDD_MDM";
+ ti,shunt-resistor-mohm = <20>;
+ };
+ };
+
+ };
+};