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| author | Sudeep Holla <sudeep.holla@arm.com> | 2015-05-07 15:45:05 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2015-05-12 16:39:50 +0200 |
| commit | 51ef519cbd4c9d7478c4050845ffb1cdc4e70fc1 (patch) | |
| tree | 7871c93d8e6a8573398bcf13945c61db22fdaa3e /arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | |
| parent | 613880a1218286eb2d6b1cf5a574241eec32e7aa (diff) | |
ARM: vexpress/tc2: Add interrupt-affinity to the PMU node
Commit 9fd85eb502a7 ("ARM: pmu: add support for interrupt-affinity
property") added an optional "interrupt-affinity" property, to specify
the CPU affinity for each SPI listed in the interrupts property.
Without this property, we get this boot warning:
CPU PMU: Failed to parse <no-node>/interrupt-affinity[0]
This patch adds interrupt-affinity to the PMU node in the
vexpress-ca15_a7(a.k.a TC2) device tree.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts')
| -rw-r--r-- | arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index 7a2aeacd62c0..107395c32d82 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -191,6 +191,7 @@ compatible = "arm,cortex-a15-pmu"; interrupts = <0 68 4>, <0 69 4>; + interrupt-affinity = <&cpu0>, <&cpu1>; }; oscclk6a: oscclk6a { |