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| author | Alex Wilson <alex.david.wilson@gmail.com> | 2015-07-17 20:23:55 -0600 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2015-07-31 10:50:05 +0200 |
| commit | 6de663fe33b35fc95e751f907aa28e608c38f121 (patch) | |
| tree | 0f7a95287fda0acd70d22a461b529f6707d37c10 /arch/arm/boot/dts/zynq-7000.dtsi | |
| parent | 1837649fd350bf25e20d05dbdd4449160ad0219b (diff) | |
ARM: zynq: DT: Add missing interrupt for L2 pl310
Add pl310 interrupt to the Zynq devicetree.
Signed-off-by: Alex Wilson <alex.david.wilson@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/boot/dts/zynq-7000.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/zynq-7000.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index d373b3860333..ac0a6a09b652 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -139,6 +139,7 @@ L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; + interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; |