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authorMax Krummenacher <max.krummenacher@toradex.com>2017-11-20 21:27:49 +0100
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2020-02-09 22:45:43 +0100
commite6558c508b63acf547479971aba6a2793f70965d (patch)
tree042be33393c341491084dc85ef3c07f02b676752 /arch/arm/boot/dts
parent337620733dd09455ef51e551c7bc9daa97ba9081 (diff)
ARM: dts (ds): imx6ull: fix pwm clock
All PWM clock instances have their clock gate. Add these consistently. Fixes freezing the kernel when one of these instances is used with IMX6UL_CLK_DUMMY as its clock source. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Stefan Agner <stefan.agner@toradex.com> (cherry picked from commit cd5d7ba49df7918732915a31bfc0f72827bebc2c) (cherry picked from commit c6306e84601b15ee0152625757aab942fa2f2d28)
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/imx6ull.dtsi24
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
index e93eec68251c..2fd9dacbbeeb 100644
--- a/arch/arm/boot/dts/imx6ull.dtsi
+++ b/arch/arm/boot/dts/imx6ull.dtsi
@@ -486,8 +486,8 @@
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
reg = <0x02084000 0x4000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6UL_CLK_DUMMY>,
- <&clks IMX6UL_CLK_DUMMY>;
+ clocks = <&clks IMX6UL_CLK_PWM2>,
+ <&clks IMX6UL_CLK_PWM2>;
clock-names = "ipg", "per";
#pwm-cells = <3>;
};
@@ -506,8 +506,8 @@
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
reg = <0x0208c000 0x4000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6UL_CLK_DUMMY>,
- <&clks IMX6UL_CLK_DUMMY>;
+ clocks = <&clks IMX6UL_CLK_PWM4>,
+ <&clks IMX6UL_CLK_PWM4>;
clock-names = "ipg", "per";
#pwm-cells = <3>;
};
@@ -837,8 +837,8 @@
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
reg = <0x020f0000 0x4000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6UL_CLK_DUMMY>,
- <&clks IMX6UL_CLK_DUMMY>;
+ clocks = <&clks IMX6UL_CLK_PWM5>,
+ <&clks IMX6UL_CLK_PWM5>;
clock-names = "ipg", "per";
#pwm-cells = <3>;
};
@@ -847,8 +847,8 @@
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
reg = <0x020f4000 0x4000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6UL_CLK_DUMMY>,
- <&clks IMX6UL_CLK_DUMMY>;
+ clocks = <&clks IMX6UL_CLK_PWM6>,
+ <&clks IMX6UL_CLK_PWM6>;
clock-names = "ipg", "per";
#pwm-cells = <3>;
};
@@ -857,8 +857,8 @@
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
reg = <0x020f8000 0x4000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6UL_CLK_DUMMY>,
- <&clks IMX6UL_CLK_DUMMY>;
+ clocks = <&clks IMX6UL_CLK_PWM7>,
+ <&clks IMX6UL_CLK_PWM7>;
clock-names = "ipg", "per";
#pwm-cells = <3>;
};
@@ -867,8 +867,8 @@
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
reg = <0x020fc000 0x4000>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6UL_CLK_DUMMY>,
- <&clks IMX6UL_CLK_DUMMY>;
+ clocks = <&clks IMX6UL_CLK_PWM8>,
+ <&clks IMX6UL_CLK_PWM8>;
clock-names = "ipg", "per";
#pwm-cells = <3>;
};