MGS-3705-1 gpu: dts: enable gpu devices for imx6

set GPU baseAddress with 256M on IMX6Q and iMX6QP,
add reserved cma in DTB to support different size,
the default cma size is 320M on all imx6 boards.

integrated patches from imx_4.9.y:
1.MGS-955 GPU:Integrate GPU module
 commit: 73183c14a20d4f1d02317f80db3d90b3be1546fc
2.MGS-1211 gpu: add GPU for 6sl,6sx,6dl
 commit: 80a8994c47cbb97fb31ef0efab92ddb29002448e
3.MGS-1087 gpu: Move the GPU reserved memory to DTS file
 commit: ea0111da6892b52c790da607a3d91140d1ebf936
4.MGS-2540 [#ccc] Need set baseAddress with RAM start address on IMX6Q
 commit: de838d99d9264884cbaaa601ab323a70b62634d9

Signed-off-by: Xianzhong <xianzhong.li@nxp.com>

4 files changed, 133 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 0277a7e0f000..c1774c9cfcec 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -63,6 +63,20 @@
 		};
 	};
 
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x14000000>;
+			linux,cma-default;
+		};
+	};
+
 	soc {
 		busfreq {
 			compatible = "fsl,imx_busfreq";
@@ -80,6 +94,26 @@
 			fsl,max_ddr_freq = <400000000>;
 		};
 
+		gpu: gpu@00130000 {
+			compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu";
+			reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
+			      <0x0 0x0>, <0x0 0x8000000>;
+			reg-names = "iobase_3d", "iobase_2d",
+				    "phys_baseaddr", "contiguous_mem";
+			interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>,
+				     <0 10 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "irq_3d", "irq_2d";
+			clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, <&clks IMX6QDL_CLK_GPU3D_AXI>,
+				 <&clks IMX6QDL_CLK_GPU2D_CORE>, <&clks IMX6QDL_CLK_GPU3D_CORE>,
+				 <&clks IMX6QDL_CLK_DUMMY>;
+			clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk",
+				      "gpu2d_clk", "gpu3d_clk",
+				      "gpu3d_shader_clk";
+			resets = <&src 0>, <&src 3>;
+			reset-names = "gpu3d", "gpu2d";
+			power-domains = <&gpc 1>;
+		};
+
 		ocram: sram@00905000 {
 			compatible = "mmio-sram";
 			reg = <0x00905000 0x1B000>;
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 63119e8eafb7..6e7d5afbe87b 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -84,6 +84,20 @@
 		};
 	};
 
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x14000000>;
+			linux,cma-default;
+		};
+	};
+
 	soc {
 		busfreq: busfreq {
 			compatible = "fsl,imx_busfreq";
@@ -96,6 +110,29 @@
 			fsl,max_ddr_freq = <528000000>;
 		};
 
+                gpu: gpu@00130000 {
+			compatible = "fsl,imx6q-gpu";
+			reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
+			      <0x02204000 0x4000>, <0x10000000 0x0>,
+			      <0x0 0x8000000>;
+			reg-names = "iobase_3d", "iobase_2d",
+				    "iobase_vg", "phys_baseaddr",
+				    "contiguous_mem";
+			interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>,
+				     <0 10 IRQ_TYPE_LEVEL_HIGH>,
+				     <0 11 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "irq_3d", "irq_2d", "irq_vg";
+			clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, <&clks IMX6QDL_CLK_OPENVG_AXI>,
+				 <&clks IMX6QDL_CLK_GPU3D_AXI>, <&clks IMX6QDL_CLK_GPU2D_CORE>,
+				 <&clks IMX6QDL_CLK_GPU3D_CORE>, <&clks IMX6QDL_CLK_GPU3D_SHADER>;
+			clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
+				      "gpu3d_axi_clk", "gpu2d_clk",
+				      "gpu3d_clk", "gpu3d_shader_clk";
+			resets = <&src 0>, <&src 3>, <&src 3>;
+			reset-names = "gpu3d", "gpu2d", "gpuvg";
+			power-domains = <&gpc 1>;
+		};
+
 		ocram: sram@00905000 {
 			compatible = "mmio-sram";
 			reg = <0x00905000 0x3B000>;
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index d72503ee91d7..a3355e579e7c 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -86,6 +86,20 @@
 		};
 	};
 
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x14000000>;
+			linux,cma-default;
+		};
+	};
+
 	intc: interrupt-controller@00a01000 {
 		compatible = "arm,cortex-a9-gic";
 		#interrupt-cells = <3>;
@@ -1021,6 +1035,24 @@
 				reg = <0x021d8000 0x4000>;
 				status = "disabled";
 			};
+
+			gpu: gpu@02200000 {
+				compatible = "fsl,imx6sl-gpu", "fsl,imx6q-gpu";
+				reg = <0x02200000 0x4000>, <0x02204000 0x4000>,
+					  <0x80000000 0x0>, <0x0 0x8000000>;
+				reg-names = "iobase_2d", "iobase_vg",
+						"phys_baseaddr", "contiguous_mem";
+				interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>, <0 11 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "irq_2d", "irq_vg";
+				clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
+						<&clks IMX6SL_CLK_MMDC_ROOT>,
+						<&clks IMX6SL_CLK_GPU2D_OVG>;
+				clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
+						  "gpu2d_clk";
+				resets = <&src 3>, <&src 3>;
+				reset-names = "gpu2d", "gpuvg";
+				power-domains = <&gpc 1>;
+			};
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 2edeee13a908..152926d500e5 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -101,6 +101,20 @@
 		};
 	};
 
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x14000000>;
+			linux,cma-default;
+		};
+	};
+
 	intc: interrupt-controller@00a01000 {
 		compatible = "arm,cortex-a9-gic";
 		#interrupt-cells = <3>;
@@ -253,6 +267,22 @@
 			external-pin-tamper = "disabled";
 		};
 
+		gpu3d: gpu3d@01800000 {
+			compatible = "fsl,imx6sx-gpu", "fsl,imx6q-gpu";
+			reg = <0x01800000 0x4000>, <0x80000000 0x0>,
+				<0x0 0x8000000>;
+			reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem";
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "irq_3d";
+			clocks = <&clks IMX6SX_CLK_GPU_AXI_PODF>, <&clks IMX6SX_CLK_GPU>,
+				<&clks 0>;
+			clock-names = "gpu3d_axi_clk", "gpu3d_clk",
+				"gpu3d_shader_clk";
+			resets = <&src 0>;
+			reset-names = "gpu3d";
+			power-domains = <&gpc 1>;
+		};
+
 		gpmi: gpmi-nand@01806000{
 			compatible = "fsl,imx6sx-gpmi-nand";
 			#address-cells = <1>;