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authorThor Thayer <tthayer@opensource.altera.com>2016-02-10 13:26:22 -0600
committerBorislav Petkov <bp@suse.de>2016-02-11 12:29:38 +0100
commitd31e2e846b35370a2317a211a50d8248d46fc83b (patch)
treede2c7adaec23e7c20ab02b25692514fca7fa36fc /arch/arm/boot
parentc3eea1942a16db52ebea0382bd5826f75b9b7e9b (diff)
ARM: dts: Add Altera L2 Cache and OCRAM EDAC entries
Add the device tree entries and bindings needed to support the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon an earlier patch to declare and setup On-chip RAM properly: 8b907c8b62ac ("arm: dts: socfpga: Add OCRAM node") Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Acked-by: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: galak@codeaurora.org Cc: grant.likely@linaro.org Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: ijc+devicetree@hellion.org.uk Cc: Kumar Gala <galak@codeaurora.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux@arm.linux.org.uk Cc: linux-doc@vger.kernel.org Cc: linux-edac <linux-edac@vger.kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: m.chehab@samsung.com Cc: Pawel Moll <pawel.moll@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Russell King <linux@arm.linux.org.uk> Link: http://lkml.kernel.org/r/1455132384-17108-2-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 3ed4abdaaa9c..15cbc747c242 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -656,6 +656,26 @@
status = "disabled";
};
+ eccmgr: eccmgr@ffd08140 {
+ compatible = "altr,socfpga-ecc-manager";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ l2-ecc@ffd08140 {
+ compatible = "altr,socfpga-l2-ecc";
+ reg = <0xffd08140 0x4>;
+ interrupts = <0 36 1>, <0 37 1>;
+ };
+
+ ocram-ecc@ffd08144 {
+ compatible = "altr,socfpga-ocram-ecc";
+ reg = <0xffd08144 0x4>;
+ iram = <&ocram>;
+ interrupts = <0 178 1>, <0 179 1>;
+ };
+ };
+
L2: l2-cache@fffef000 {
compatible = "arm,pl310-cache";
reg = <0xfffef000 0x1000>;