diff options
author | Fugang Duan <b38611@freescale.com> | 2015-08-18 15:55:26 +0800 |
---|---|---|
committer | Octavian Purdila <octavian.purdila@nxp.com> | 2017-02-23 14:21:42 +0200 |
commit | 3c9a18fd97ea0d7a15207c404654de8a8ad0175d (patch) | |
tree | b816a958673b5ac9790917569d505a5a117c40af /arch/arm/boot | |
parent | f406de3b220c59d8abf9214f5ee3c7f8ec0f4554 (diff) |
MLK-11374: ARM: dts: add NAND support for i.MX6UL ddr3 arm2 board
Add GPMI NAND support for i.MX6UL 14x14 ddr3 arm2 board.
Signed-off-by: Han Xu <b45815@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r-- | arch/arm/boot/dts/Makefile | 3 | ||||
-rw-r--r-- | arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-gpmi-weim.dts | 34 |
2 files changed, 36 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 1f8c96832af2..f46a8bd19094 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -424,7 +424,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ - imx6ul-14x14-ddr3-arm2.dtb + imx6ul-14x14-ddr3-arm2.dtb \ + imx6ul-14x14-ddr3-arm2-gpmi-weim.dtb dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-cl-som-imx7.dtb \ imx7d-colibri-eval-v3.dtb \ diff --git a/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-gpmi-weim.dts b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-gpmi-weim.dts new file mode 100644 index 000000000000..2e6b54495d05 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-gpmi-weim.dts @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-ddr3-arm2.dts" + +/* + * solve pin conflict with NAND + * + * USDHC2_CD, SD2_RST_B, USDHC2_WP conflict with RAWNAND CE pins , also + * overwritten the conflict of SD2_RST_B with RAWNAND ALE in hog + * QSPI CLK, CE and DATA pins conflict with RAWNAND data pins and CE, CLE, RB, + * WP, DQS pin + * + */ +&iomuxc { + pinctrl-0 = <&pinctrl_hog>; +}; + +&qspi{ + status = "disabled"; +}; + +&gpmi{ + status = "okay"; +}; + +&usdhc2 { + status = "disabled"; +}; |