diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2017-11-20 21:27:49 +0100 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-12-21 14:31:43 +0100 |
| commit | 9282ed58a8d84776f995225f1b3d2e793d0bdb50 (patch) | |
| tree | ae3230e745111b764e187bd94ac477e613c4edc0 /arch/arm/boot | |
| parent | 1fd569d635de4e987a1db2bc1ffb5a7193c46a77 (diff) | |
ARM: dts: imx6ull: fix pwm clock
All PWM clock instances have their clock gate. Add these consistently.
Fixes freezing the kernel when one of these instances is used with
IMX6UL_CLK_DUMMY as its clock source.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit 4bc835895a461a17387b52a8229a4b7a4a52d982)
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/imx6ull.dtsi | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index ad5188b8697e..00208c3b778b 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -447,8 +447,8 @@ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_DUMMY>; + clocks = <&clks IMX6UL_CLK_PWM2>, + <&clks IMX6UL_CLK_PWM2>; clock-names = "ipg", "per"; #pwm-cells = <3>; }; @@ -467,8 +467,8 @@ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_DUMMY>; + clocks = <&clks IMX6UL_CLK_PWM4>, + <&clks IMX6UL_CLK_PWM4>; clock-names = "ipg", "per"; #pwm-cells = <3>; }; @@ -798,8 +798,8 @@ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x020f0000 0x4000>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_DUMMY>; + clocks = <&clks IMX6UL_CLK_PWM5>, + <&clks IMX6UL_CLK_PWM5>; clock-names = "ipg", "per"; #pwm-cells = <3>; }; @@ -808,8 +808,8 @@ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x020f4000 0x4000>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_DUMMY>; + clocks = <&clks IMX6UL_CLK_PWM6>, + <&clks IMX6UL_CLK_PWM6>; clock-names = "ipg", "per"; #pwm-cells = <3>; }; @@ -818,8 +818,8 @@ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x020f8000 0x4000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_DUMMY>; + clocks = <&clks IMX6UL_CLK_PWM7>, + <&clks IMX6UL_CLK_PWM7>; clock-names = "ipg", "per"; #pwm-cells = <3>; }; @@ -828,8 +828,8 @@ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x020fc000 0x4000>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_DUMMY>; + clocks = <&clks IMX6UL_CLK_PWM8>, + <&clks IMX6UL_CLK_PWM8>; clock-names = "ipg", "per"; #pwm-cells = <3>; }; |